Spice Modeling Engineer

Spice Modeling Engineer

Job Details:

Job Description: 

The Role and Impact As a Senior Spice Modeling Engineer, you will own the development, validation, and strategic direction of SPICE models that enable Intel's advanced process technologies. You will define modeling methodologies, resolve complex customer and cross-team technical issues, and drive improvements to modeling infrastructure and tools across the organization. Business Group You will join Intel's Design Technology Platform (DTP) - Process Design Kit (PDK) team. This team develops and delivers the technology, tools, and methodologies required for efficient, high-quality design across Intel products. Working closely with Technology Development, Product Design teams, and EDA partners, the group drives design enablement for Intel's latest process technologies. Key Responsibilities - Own and drive development of SPICE model files for advanced process nodes, partnering directly with Extraction, Technology Development, and Library leads to resolve complex technical trade-offs - Define and drive automation strategy for QA flows to improve validation coverage, efficiency, and scalability across the team - Architect and optimize test structures for model-to-hardware correlation and parasitic extraction, setting standards for the broader team - Author and own documentation, guidelines, and training materials that establish best practices across the org - Define methodologies to extract SPICE model parameters from IV and CV data, and represent the team in technical sign-off discussions with internal and external stakeholders - Partner with technology development and design engineering leadership to shape circuit tools, compact model strategy, and process file direction - Provide technical mentorship to junior engineers and contribute to team technical roadmap

Qualifications:

Minimum Qualifications
Master's degree with 6+ years of experience, or PhD with 3+ years of experience, in Electrical Engineering, Microelectronics, or a related field with a focus on semiconductor device physics, including substantial hands-on experience developing, validating, and driving sign-off of compact/SPICE models within a foundry PDK environment.

Preferred Qualifications
1. Demonstrated track record of leading compact modeling methodology decisions (e.g., model sign-off criteria, extraction methodology) at advanced/leading-edge process nodes
2. Strong Python scripting skills, with experience building or owning modeling automation infrastructure
3. Experience representing technical work to customers, cross-functional leadership, or external partners
4. Excellent written and verbal communication skills, with demonstrated ability to align cross-org stakeholders on technical direction

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.