Functional Verification Engineer

Functional Verification Engineer

Project Role : Functional Verification Engineer
Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills : SoC Verification
Good to have skills : NA
Minimum 3 year(s) of experience is required
Educational Qualification : 15 years full time education

Summary:
As a Functional Verification Engineer, a typical day involves designing and implementing comprehensive testbenches to validate the functional accuracy of digital designs at both block and system levels. The role requires creating various types of tests, including constrained-random, directed, and coverage-driven, to thoroughly assess the design's behavior. Collaboration with design and architecture teams is essential to uncover edge cases and guarantee exhaustive functional coverage prior to tape-out. This position demands a proactive approach to problem-solving and continuous communication within the team to ensure the highest quality of verification outcomes.

Roles & Responsibilities:
- Expected to perform independently and become an SME.
- Required active participation/contribution in team discussions.
- Contribute in providing solutions to work related problems.
- Develop and maintain verification environments to support design validation efforts.
- Analyze verification results and debug issues to improve test coverage and quality.
- Support junior team members by sharing knowledge and assisting in their development.

Professional & Technical Skills:
- Must To Have Skills: Proficiency in SoC Verification.
- Experience with verification methodologies and languages such as SystemVerilog and Universal Verification Methodology.
- Strong understanding of digital design principles and hardware description languages.
- Ability to develop constrained-random and directed test scenarios to achieve comprehensive coverage.
- Familiarity with coverage-driven verification techniques and tools.
- Skilled in debugging and analyzing simulation results to identify design issues.

Additional Information:
- The candidate should have minimum 3 years of experience in SoC Verification.
- This position is based at our BDC6F - SEZ office.
- A 15 years full time education is required.