Silicon DFT Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 2 years of experience with analog or mixed-signal Integrated Circuit (IC) design.
• Experience with system-on-chip design/integration flow, and design automation.
• Experience with Design for Test (DFT) technologies such as Scan, Algorithmic Test Pattern Generation (ATPG) and Memory Built in Self Test (MBIST).
• Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, STA, simulation, and verification flow.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
• Experience working with Automatic Test Equipment (ATE) engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
• Experience in System on a Chip (SoC) cycles, including silicon bring-up and silicon debug activities.
• Experience in fault modeling.

About the job

Responsibilities

• Document Design for Testability (DFT) architecture and test sequences, including boot-up sequence associated with test pins.
• Participate in DFT logic insertion like scan and BIST at Register-Transfer Level (RTL) and netlist level.
• Perform DFT checks for scan coverage and memory Built-In Self Test (BIST).
• Plan SoC/IP/Subsystems (SS) DFT and collaborate with cross-functional teams, DFT constraints development for timing closure and Physical Design (PD)/Static Timing Analysis (STA) support.
• Perform quality check flows like Lint, Clock Domain Crossing (CDC) of the DFT RTL in DFT modes. Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams.