Principal Engineer, High‑Speed RTL Design

Key Responsibilities 

High‑Speed RTL Design & Implementation 

• Design and implement timing‑critical RTL blocks, including:  

• Control and sequencing FSMs 

• Power‑up, shutdown, and mode‑transition logic 

• Register banks and configuration logic 

• Telemetry and monitoring datapath 

• Develop RTL with attention to latency, deterministic behavior, race‑free logic, and metastability avoidance. 

 Nanometer‑Process‑Aware RTL Coding 

• Write RTL that is robust to:  

• Tight setup and hold margins 

• Clock skew and uncertainty 

• Multi‑cycle and false‑path constraints 

• Process, voltage, and temperature (PVT) variation 

• Ensure RTL is clean for synthesis, static timing analysis, and ECO cycles in sophisticated technology nodes. 

Clocking, Reset & Power‑Aware Logic 

• Implement and review clock‑domain crossings (CDC) using proven synchronization techniques. 

• Design reset and initialization logic to ensure predictable system startup and recovery. 

• Support power‑aware and mode‑dependent behavior as the need arises by system operation. 

Integration & Debug 

• Integrate RTL blocks into larger subsystems or top‑level designs, resolving:  

• Port‑list mismatches 

• Clock and reset dependencies 

• Mode interaction issues 

• Debug RTL and integration issues using simulation waveforms and tool feedback. 

Verification & Timing Closure Support 

• Work closely with verification engineers to:  

• Clarify design intent and corner cases 

• Fix RTL issues uncovered during verification 

• Address timing issues identified during synthesis or place‑and‑route by refining logic, simplifying control paths, or adding limited pipelining under guidance. 

Design Reviews & Documentation 

• Participate actively in RTL and design reviews, incorporating feedback from senior engineers. 

• Maintain clear documentation describing block functionality, assumptions, and known limitations. 

Required Technical Skills 

RTL & Digital Design 

• Strong proficiency in SystemVerilog / Verilog RTL 
  

Experience with:  

• FSM design and implementation

• Reset synchronization 

• Clock‑domain crossing concepts 

• Solid understanding of timing‑critical control logic. 

High‑Speed & System Awareness 

Solid understanding of:  

• Setup/hold timing fundamentals 

• Critical‑path sensitivity 

• Multi‑mode and settings‑based behavior  

• Exposure to mixed‑signal interaction (digital logic controlling or responding to analog behavior). 

Flow Awareness 

• Familiarity with:

• RTL lint and CDC checks 

• Synthesis and basic STA reports 

• DFT‑friendly RTL practices 

• UPF and LEC 

• Ability to debug issues exposed during RTL sign‑off or late integration stages. 

Good‑to‑Have or equivalent experience  

• Experience with PMICs, mixed‑signal SoCs, or companion ICs

• Exposure to industry-standard specifications  

• Basic scripting skills (Python / Tcl) for automation 

• Experience working across RTL–DV–PD handshakes 

• Apply AI-enabled engineering tools

Behavioral Expectations 

• Works independently on assigned RTL modules or subsystems 

• Raises risks early with analysis and proposed solutions 

• Demonstrates growing ownership of RTL quality and delivery 

• Learns from reviews and feedback to deepen high‑speed design expertise 

• Effective and compliant use of Micron‑approved AI tools to augment verification activities, improve execution efficiency, and support continuous improvement.